The present invention relates to an AD converter, an AD convert apparatus, and an AD convert method. For example, the present invention relates to an AD converter, an AD convert apparatus, and an AD convert method which perform successive approximation.
A successive approximation register (SAR) ADC (SAR-ADC) is known as an ADC (an A/D converter: an analog/digital converter) that converts an input analog signal into a digital signal. The SAR-ADC mainly includes a DAC (a D/A converter: a digital/analog converter), a comparator, and a successive approximation logic circuit. The SAR-ADC performs AD conversion by sampling and holding an input analog signal and performing a successive approximation operation on the input analog signal, and outputs a digital signal as a result of the successive approximation. As a related art of the SAR-ADC, for example, H. Lee et. al., “A Self-Calibrating 15 bit CMOS A/D Converter”, IEEE Solid State Circuits, vol. sc-19, No. 6, December 1984 (hereinafter referred to as “Non Patent Literature 1”); Hideo Nakane et. al., “A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile”, ASSOC, Session 5-2 November 2013 (hereinafter referred to as “Non Patent Literature 2”); Japanese Unexamined Patent Application Publication No. H05-167449; and Japanese Patent Nos. 3224808, 4806021, 4890561, and 5565169 are known.
To achieve an accuracy required for a high-accuracy SAR-ADC, a high relative accuracy is required for analog elements (capacitors and resistors) constituting a built-in DAC. However, to achieve, for example, a 14-bit or higher ADC, the device size necessary for securing the relative accuracy (pair accuracy) of the analog elements increases. Accordingly, in the ADC of the related art, it is necessary to increase the relative accuracy by increasing the element area.
Non Patent Literature 1 discloses an ADC that calibrates errors in analog elements so as to increase the relative accuracy of the analog elements. Non Patent Literature 1, Japanese Unexamined Patent Application Publication No. H05-167449, and Japanese Patent No. 5565169 employ a technique in which a mismatch between elements is obtained as a digital value and the digital value is fed back in an analog fashion during AD conversion processing.
Non Patent Literature 2 discloses a digital correction ADC that uses a non-binary-weighted capacitive DAC and an LMS (Least Mean Square) engine. Non Patent Literature 2 and Japanese Patent. No. 3224808 employ a technique in which a result of a mismatch between elements is obtained as a digital value and the digital value is corrected in a digital fashion after AD conversion. Japanese Patent No. 3224808 discloses an example of the digital correction in which the technique disclosed in Non Patent Literature 1 is applied to a non-binary-weighted DAC with redundancy.
In addition, Japanese Patent Nos. 4806021 and 4890561 disclose an ADC to reduce thermal noise.